1. Field of the Invention
The present invention relates to a control circuit that supplies a control signal to an image signal line driving circuit and a scan line driving circuit that drives a liquid crystal panel (the control circuit is hereinafter referred to as timing controller). The invention also relates to a liquid crystal display using the timing controller.
2. Description of the Related Art
FIG. 4 is a waveform diagram showing main input/output waveforms when a timing controller of a conventional liquid crystal display is under normal operation.
FIG. 5 is a waveform diagram showing input/output waveforms when the timing controller of the conventional liquid crystal display is under abnormal operation. FIG. 5 shows an example of a signal in a case where the timing controller generates a signal that may break down a power circuit of the liquid crystal display due to any drive different from normal drive in the circuit arranged on the input side of the timing controller or due to any malfunction.
In FIGS. 4 and 5, axis of ordinates of each waveform indicates voltage, and axis of abscissas indicates time. In the drawings, image data supplied to picture elements of liquid crystal panel are omitted.
Referring to FIG. 4, numerals 1a to 3a designate signals inputted to a timing controller. Reference numeral 1a designates a horizontal synchronizing signal (HD) used as a reference signal for synchronizing the liquid crystal display in horizontal direction. Numeral 2a designates a vertical synchronizing signal (VD) used as a reference signal for synchronizing the liquid crystal display in vertical direction. Numeral 3a designates a data enable signal (DENA) showing a period during which the image data are effective. Further, numerals 4a to 8a designate signals outputted by the timing controller, numerals 4a to 6a designate signals for controlling the image signal line driving circuit, and numerals 7a to 8a designate signals for controlling scan line driving circuit. Numeral 4a designates a start pulse (STH) that indicates a start of image data in horizontal direction, and numeral 5a designates a polarity inversion signal (POL) for inverting polarity of liquid crystal drive. Numeral 6a designates a latch pulse (LP) for transferring image data to an output side of the image signal line driving circuit. Clocks used for signal processing in the image signal line driving circuit and the timing controller are omitted herein. Further, numeral 7a designates a clock (CLKV) for signal processing in the scan line driving circuit, and numeral 8a designates a start pulse (STV) that indicates start of vertical scanning in the scan line driving circuit.
In FIG. 5, numerals 1b to 8b designate signals respectively corresponding to numerals 1a to 8a in FIG. 4.
Additionally, the image signal line driving circuit is normally cascade-connected, and in which the start pulse (STH) signal is delivered sequentially to an adjacent circuit for picture elements, thus control being made for each scan line.
The scan line driving circuit is likewise normally cascade-connected, and in which the start pulse (STV) signal is sequentially delivered to an adjacent circuit for scan lines, thus control being made for each scan line.
The output signals 4a to 8a are normally generated in the timing controller on the basis of inputted signals 1a to 3a. Therefore, as long as the inputted signals 1a to 3a are loaded into the timing controller in the timing relation necessary for image display, the timing controller can transmit a normal signal to the image signal line driving circuit and the scan line driving circuit under the normal operating conditions.
However, in the case of any drive different from normal one in the circuit arranged on the input side of the timing controller or any malfunction, otherwise due to any problem in characteristics of transmission line up to transmission of the signal inputted to the timing controller, sometimes the inputted signals 1a to 3a may get out of normal timing relation. Moreover, the circuit arranged on the input side of the timing controller may transmit any signal getting out of a predetermined specification of the timing controller due to any mistake or error. In this manner, when the input signals 1a to 3a are inputted in any abnormal timing relation, the output signals 4a to 8a generated in the timing controller may not be outputted normally or unexpected abnormal waveforms may be outputted.
For example, when signals are inputted at the timing of the inputted signals 1b to 3b shown in FIG. 5, output signals 4b to 8b may be outputted. FIG. 5 shows an example that the timing controller outputs irregular waveforms because of irregular signals inputted to the timing controller. It is of course possible to cope with the irregularity, i.e., abnormal output by detecting the irregular waveforms using any other circuit or forcedly changing the display mode, in the case that such irregular relation as input signals 1b to 3b continues for a long time. However, if the irregular state continues for a very short time displaying one picture or so, it is often the case that such a short time of irregular state is ignored.
In the example shown in FIG. 5, there is few possibility of effecting negatively on a liquid crystal display in most case. However, if signals being in the relation of output signals 7b and 8b are given to the scan line driving circuit, the scan line driving circuit drives a plurality of scan lines simultaneously. As a result, a considerable load may be imposed on the power circuit for driving liquid crystal panel. In the worst case, the considerable load causes stop and/or breakdown of the power circuit, and there is a possibility that the display of the liquid crystal panel cannot be restored even after the signal has returned to normal operating conditions.
In the Japanese Patent Publication (unexamined) No. 2001-109424 (pages 5 to 8 and 10, FIG. 2),to cope with malfunction in signal due to abnormality in flexible cable for connection between a liquid crystal display control section and a liquid crystal display module, a signal management and control section is arranged in a scanning driver. This arrangement, however, is not a countermeasure to abnormal input signal in the control circuit.